As Digital Television (DTV) expands worldwide and gradually dominates the TV market, the demand for flexible architecture and scalable computation will become greater. The impetus to adopt flexible architecture is lead by the availability of a more powerful digital signal processing central processing unit (DSPCPU) core and the increasing demand for new functionality. As the computational power of the DSPCPU core increases over time, video-processing functions will tend to migrate from hardware implementations on coprocessors to software implementations on the DSPCPU core. At the same time, the emergence of new audio/visual processing functionality will mandate the application of coprocessors.
Software implementation of audio/video processing functions on the DSPCPU core, creates opportunities for algorithm scalability by allowing trade-off between the usage of available computational resources (i.e. CPU cycles, cache, memory size, memory bandwidth, coprocessor load, etc.) and subjective image quality. Although the DSPCPU core is getting more and more powerful, reducing cost by constraining CPU usage while still generating satisfactory results is a big challenge for video algorithm designs driven by consumer electronics.
The application of scalable video algorithms (SVAs) will allow multiple video functions to run concurrently on the DSPCPU core and the coprocessors while the total computational resources are on constraint. SVAs can also lead to the reduction of coprocessors and other external hardware. The system cost is then reduced with smaller silicon area of the multimedia processor chip.
One potential application for SVAs is in video decoders. Video decoders should be capable of decoding incoming compressed digital video signals at real-time speed. In a typical application such as a set-top box, the computational resource available for video decoding varies over time because the total available resource has to be divided among many different tasks. When the computational resource available at any given time is insufficient, the decoder should then intelligently adapt the complexity of the decoding algorithm, albeit, with some loss in the visual quality of the decoded video.
The most prevalently used compression techniques for digital video and images are MPEG and JPEG respectively. Both these techniques use the block based DCT as one of the basic blocks in the compression. A video decoder performs the following algorithmic steps in decoding video: variable length decoding, inverse quantization, inverse DCT (IDCT) and motion compensation. The IDCT requires a substantial portion of the computational resource and by using an approximate algorithm its complexity can be adapted to scale to the available resource.
Techniques to reduce the IDCT complexity based on input data are known. These techniques classify the input data into different categories and use different IDCT algorithms of varying complexities for different categories of data. However such techniques have the additional overhead of classifying the input data into the selected categories.
Accordingly, a need exists for an IDCT having a complexity which scales to the computational resources available in the microprocessor of the decoder at any given time and which is input data-independent.